With the continuous development of integrated circuit manufacturing technology and the improvement of the integrated level of the chip, three-dimension and multi-layer configuration is widely used in back-end interconnect. Meanwhile, copper interconnects become the mainstream interconnect technology in the manufacture of integrated circuit because it has lower resistivity, better anti-migration, and it's more conducive to increase device density than aluminum, more conductive to increase the clock frequency, more conductive to reduce power consumption and cost. The Damascene process works as the essential technology of realizing multilayer copper metal interconnection comprising a series of process: insulator dielectric layer deposition process; trench & contact hole etch; depositing of metal diffusion barrier layer and copper seed layer; Electrochemical Plating (ECP) craft of copper; Chemical Mechanical Polishing (CMP) of copper, etc. Among them, the CMP which works as a unique global planarization process is a key technology of realizing copper interconnects.
But the surface morphology, the copper connectivity and the thickness of the insulating dielectric layer exist very related variation with the layout Post-CMP. As FIG. 1 illustrated, some area such as high density area of wide line or graphics will appear in phenomenon like dishing defect or erosion, which become the serious flaws of affecting the flatness of Post-CMP.
The surface profile post-ECP, the grinding characteristics of CMP, the Surface material of chip and many other factors will affect the profile of Post-CMP. Thereinto, the ECP profile and the grinding characteristics of CMP are directly affected by the graphical features of metal wire's area density, line width, spacing, etc, which result in the strong correlation between dishing defect of Post-CMP, erosion and graphics. The cross-sectional area of interconnect line will reduce and the resistance value will increases because of the dishing defect and the erosion defect.
The studies show that in the case of different spacing distance and line width the influence of dishing defect on the resistance of the interconnect lines is from 28.7% to 31.7% and the influence on the resistance also becomes large with the increase of line width. In addition, as FIG. 2 illustrated, post-CMP profile of the back metal layer (metal 2 showed in the figure) will become more uneven due to the dishing defect and erosion of the preceding metal layer and form so-called Laminated effect. Such effect will be worse with the increase of metal layer number, which will cause insurmountable difficulties in technology and integration, and affect the yield and the reliability of the product.
The development of the prior art make the design for manufacturability (DFM) technology the advanced design technique of improving chip yield proposed in recent years, and it has been already supported by a variety of automated design software. Such technique feedback the various effect and variability problem that may occur in the manufacturing process to the designer, so the designer may estimate the impact of the technology to the circuit in the early time of the design and optimize the layout to make the chip yield rate meet the expected requirement ultimately.
For the defective workmanship of the Cu chemical mechanical polishing technique (Cu-CMP) mentioned above, the DFM optimization method that the current industry used usually fill dummy pattern in the graphical blank area when doing wiring design to adjust the pattern density of the layout, so the pattern density may be consistent as far as possible in every area to improve the flatness of the surface of the metal. The existing method for filling dummy pattern can be summarized into two categories: rule-based dummy fill and model-based dummy fill.
Rule-based dummy fill divide the layout into separate windows according to specific size and fill dummy pattern to windows that have too low density. It also rules that metal density of each window must be within a predetermined range. Fill fixed dummy pre-designed in the blank area of the layout that the metal density of each window and the overall to achieve the requirements of the design rules. The advantage of this filling method is: simple, the running time is short and easy to implement, the layout designers only need to follow some very simple rules. The weakness of this method is that although it may improve the overall density of the metal, but it ignores some critical factor, such as the impact of the line width to the flatness after chemical snow polishing and so on, thus we can't control the variation of the thickness of the interlayer dielectric and the metal accurately. Furthermore, the purpose of this filling method is to improve the overall metal density uniformity by maximizing the density of the metal. It totally did not consider that large number of redundant metal pattern will increase the coupling capacitor of back metal layer and it may raise issues like signal delay and power consumption increase.
Model-based dummy fill design the solution of dummy fill by establishing the surface morphology model after Cu-CMP. This approach not only need to consider raising the uniformity of overall effective density, but also need to take into account the impact of the metal dimensions and density to the surface morphology after chemical mechanical polishing, at the same time, it may also adopt design rules like minimizing density difference and minimizing dummy pattern fill in according to the simulation result of the process model and the tangible impact to the product. The main purpose of the minimizing density difference method is to minimum the difference of density between the adjacent windows, while the purpose of the minimum fill level method which minimize the dummy pattern in the filling window is to reduce the parasitic electrical effects caused by dummy pattern. Model-based dummy fill method may get better effect of flatness in nanometer process node, but owing to extraction of simulation model and complicated fill algorithm, it have high requirements on events and resources which bring non-negligible negative impact to the design cycle and cost.
No matter the method of redundancy metal filling method is rule-based or model based, both of them have their own shortcomings. The development of modern technology requires the fast and effective injection techniques of dummy pattern, which can achieve better flattening effects and avoid overly complex algorithms to ensure the reasonable use of time and resources.